tag :: hardware

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1BiKA: Binarized KAN-inspired Neural Network for Efficient Hardware Accelerator Designs
Y. Liu, S. Ullah, and A. Kumar. 2025 IEEE 33rd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), page 276-276. (May 2025)
9 days ago by @scadsfct
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BiKA
hardware
neural_network
yaff
BiKAhardwareneural_networkyaff
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1Neuromorphic hardware for sustainable AI data centers
B. Vogginger, A. Rostami, V. Jain, S. Arfa, A. Hantsch, D. Kappel, M. Schäfer, U. Faltings, H. Gonzalez, C. Liu and 1 other author(s). (2024)
8 months ago by @scadsfct
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AI
Neuromorphic
area_responsibleai
centers
data
hardware
sustainable
topic_lifescience
xack
AINeuromorphicarea_responsibleaicentersdatahardwaresustainabletopic_lifesciencexack
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2BitSys: Bitwise Systolic Array Architecture for Multi-precision Quantized Hardware Accelerators
Y. Liu, S. Ullah, and A. Kumar. 2024 IEEE 32nd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), page 220-220. (2024)
11 months ago by @yuli164c
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hardware
multiplier
myown
quantization
systolic
hardwaremultipliermyownquantizationsystolic
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2High-Flexibility Designs of Quantized Runtime Reconfigurable Multi-Precision Multipliers
Y. Liu, S. Rai, S. Ullah, and A. Kumar. IEEE Embedded Systems Letters, 15 (4): 194-197 (2023)
11 months ago by @yuli164c
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FPGA
Hardware
Multi-precision
Multiplier
Quantization
myown
FPGAHardwareMulti-precisionMultiplierQuantizationmyown
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1Memory-efficient deep learning on a SpiNNaker 2 prototype
C. Liu, G. Bellec, B. Vogginger, D. Kappel, J. Partzsch, F. Neumärker, S. Höppner, W. Maass, S. Furber, R. Legenstein and 1 other author(s). Front. Neurosci., (November 2018)
11 months ago by @scadsfct
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SpiNNaker
deep
efficient
energy
footprint
hardware
memory
parallelism
pruning
rewiring
sparsity
zno
SpiNNakerdeepefficientenergyfootprinthardwarememoryparallelismpruningrewiringsparsityzno
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1BiKA: Binarized KAN-inspired Neural Network for Efficient Hardware Accelerator Designs

1Neuromorphic hardware for sustainable AI data centers

2BitSys: Bitwise Systolic Array Architecture for Multi-precision Quantized Hardware Accelerators

2High-Flexibility Designs of Quantized Runtime Reconfigurable Multi-Precision Multipliers

1Memory-efficient deep learning on a SpiNNaker 2 prototype

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PUMA

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publications (hide)5 displayallpublications onlypublications per page5102050100 sort byadded attitleauthorpublication dateentry typehelp for advanced sorting... RSSBibTeXRDFmore...

1BiKA: Binarized KAN-inspired Neural Network for Efficient Hardware Accelerator Designs

1Neuromorphic hardware for sustainable AI data centers

2BitSys: Bitwise Systolic Array Architecture for Multi-precision Quantized Hardware Accelerators

2High-Flexibility Designs of Quantized Runtime Reconfigurable Multi-Precision Multipliers

1Memory-efficient deep learning on a SpiNNaker 2 prototype

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