This paper introduces the processing element architecture of the second generation SpiNNaker chip, implemented in 22nm FDSOI. On circuit level, the chip features adaptive body biasing for near-threshold operation, and dynamic voltage-and-frequency scaling driven by spiking activity. On system level, processing is centered around an ARM M4 core, similar to the processor-centric architecture of the first generation SpiNNaker. To speed operation of subtasks, we have added accelerators for numerical operations of both spiking (SNN) and rate based (deep) neural networks (DNN). PEs communicate via a dedicated, custom-designed network-on-chip. We present three benchmarks showing operation of the whole processor element on SNN, DNN and hybrid SNN/DNN networks.
%0 Journal Article
%1 Hoppner2021-ly
%A Höppner, Sebastian
%A Yan, Yexin
%A Dixius, Andreas
%A Scholze, Stefan
%A Partzsch, Johannes
%A Stolba, Marco
%A Kelber, Florian
%A Vogginger, Bernhard
%A Neumärker, Felix
%A Ellguth, Georg
%A Hartmann, Stephan
%A Schiefer, Stefan
%A Hocker, Thomas
%A Walter, Dennis
%A Liu, Genting
%A Garside, Jim
%A Furber, Steve
%A Mayr, Christian
%D 2021
%I arXiv
%K
%T The SpiNNaker 2 processing element architecture for hybrid digital neuromorphic computing
%X This paper introduces the processing element architecture of the second generation SpiNNaker chip, implemented in 22nm FDSOI. On circuit level, the chip features adaptive body biasing for near-threshold operation, and dynamic voltage-and-frequency scaling driven by spiking activity. On system level, processing is centered around an ARM M4 core, similar to the processor-centric architecture of the first generation SpiNNaker. To speed operation of subtasks, we have added accelerators for numerical operations of both spiking (SNN) and rate based (deep) neural networks (DNN). PEs communicate via a dedicated, custom-designed network-on-chip. We present three benchmarks showing operation of the whole processor element on SNN, DNN and hybrid SNN/DNN networks.
@article{Hoppner2021-ly,
abstract = {This paper introduces the processing element architecture of the second generation SpiNNaker chip, implemented in 22nm FDSOI. On circuit level, the chip features adaptive body biasing for near-threshold operation, and dynamic voltage-and-frequency scaling driven by spiking activity. On system level, processing is centered around an ARM M4 core, similar to the processor-centric architecture of the first generation SpiNNaker. To speed operation of subtasks, we have added accelerators for numerical operations of both spiking (SNN) and rate based (deep) neural networks (DNN). PEs communicate via a dedicated, custom-designed network-on-chip. We present three benchmarks showing operation of the whole processor element on SNN, DNN and hybrid SNN/DNN networks.},
added-at = {2024-09-10T11:56:37.000+0200},
author = {H{\"o}ppner, Sebastian and Yan, Yexin and Dixius, Andreas and Scholze, Stefan and Partzsch, Johannes and Stolba, Marco and Kelber, Florian and Vogginger, Bernhard and Neum{\"a}rker, Felix and Ellguth, Georg and Hartmann, Stephan and Schiefer, Stefan and Hocker, Thomas and Walter, Dennis and Liu, Genting and Garside, Jim and Furber, Steve and Mayr, Christian},
biburl = {https://puma.scadsai.uni-leipzig.de/bibtex/2d4ea4caf7576ac8632899708631be9f0/scadsfct},
interhash = {6f9d8bfd2a1ae30bbc52af2e9ffb03a7},
intrahash = {d4ea4caf7576ac8632899708631be9f0},
keywords = {},
publisher = {arXiv},
timestamp = {2024-09-10T15:15:57.000+0200},
title = {The {SpiNNaker} 2 processing element architecture for hybrid digital neuromorphic computing},
year = 2021
}
