Using FPGAs to Accelerate Myers Bit-Vector Algorithm
J. Hoffmann, D. Zeckzer, and M. Bogdan. XIV Mediterranean Conference on Medical and Biological Engineering and Computing 2016, page 535--541. Cham, Springer International Publishing, (2016)
Abstract
We present a proof-of-concept implementation of Myers bit-vector algorithm for approximate string matching in hardware. In terms of bit-vector operations, the algorithm is accelerated by using the massive parallel computing capabilities of a field programmable gate array (FPGA). The system is realized on an embedded platform with a high computational and energy efficiency. Compared to the fastest software implementation running on the embedded processor, the hardware achieves an overall speed-up of approximately 2 and a speed-up of approximately 8 considering the computation only.
%0 Conference Paper
%1 10.1007/978-3-319-32703-7_104
%A Hoffmann, Jörn
%A Zeckzer, Dirk
%A Bogdan, Martin
%B XIV Mediterranean Conference on Medical and Biological Engineering and Computing 2016
%C Cham
%D 2016
%E Kyriacou, Efthyvoulos
%E Christofides, Stelios
%E Pattichis, Constantinos S.
%I Springer International Publishing
%K imported
%P 535--541
%T Using FPGAs to Accelerate Myers Bit-Vector Algorithm
%X We present a proof-of-concept implementation of Myers bit-vector algorithm for approximate string matching in hardware. In terms of bit-vector operations, the algorithm is accelerated by using the massive parallel computing capabilities of a field programmable gate array (FPGA). The system is realized on an embedded platform with a high computational and energy efficiency. Compared to the fastest software implementation running on the embedded processor, the hardware achieves an overall speed-up of approximately 2 and a speed-up of approximately 8 considering the computation only.
%@ 978-3-319-32703-7
@inproceedings{10.1007/978-3-319-32703-7_104,
abstract = {We present a proof-of-concept implementation of Myers bit-vector algorithm for approximate string matching in hardware. In terms of bit-vector operations, the algorithm is accelerated by using the massive parallel computing capabilities of a field programmable gate array (FPGA). The system is realized on an embedded platform with a high computational and energy efficiency. Compared to the fastest software implementation running on the embedded processor, the hardware achieves an overall speed-up of approximately 2 and a speed-up of approximately 8 considering the computation only.},
added-at = {2024-10-02T10:38:17.000+0200},
address = {Cham},
author = {Hoffmann, J{\"o}rn and Zeckzer, Dirk and Bogdan, Martin},
biburl = {https://puma.scadsai.uni-leipzig.de/bibtex/261a82f1a9f7233cd38cfb05402394895/scadsfct},
booktitle = {XIV Mediterranean Conference on Medical and Biological Engineering and Computing 2016},
editor = {Kyriacou, Efthyvoulos and Christofides, Stelios and Pattichis, Constantinos S.},
interhash = {302924c282ae3d1b4d30b1b85b086683},
intrahash = {61a82f1a9f7233cd38cfb05402394895},
isbn = {978-3-319-32703-7},
keywords = {imported},
pages = {535--541},
publisher = {Springer International Publishing},
timestamp = {2024-10-02T10:38:17.000+0200},
title = {Using FPGAs to Accelerate Myers Bit-Vector Algorithm},
year = 2016
}
