BitSys: Bitwise Systolic Array Architecture for Multi-precision Quantized Hardware Accelerators. 2024 IEEE 32nd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 220-220, 2024. [PUMA: hardware multiplier myown quantization systolic]
High-Flexibility Designs of Quantized Runtime Reconfigurable Multi-Precision Multipliers. IEEE Embedded Systems Letters, (15)4:194-197, 2023. [PUMA: FPGA Hardware Multi-precision Multiplier Quantization myown]
NetPU-M: a Generic Reconfigurable Neural Network Accelerator Architecture for MLPs. 2023 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 85-92, 2023. [PUMA: Accelerator FPGA Quantization Reconfiguration myown]