%0 Conference Paper %1 aliagha2024dacgra %A Aliagha, Ensieh %A Charaf, Najdet %A Venkatesan, Nitin Krishna %A Göhringer, Diana %B 2024 27th Euromicro Conference on Digital System Design (DSD) %D 2024 %K imported %P 410-417 %R 10.1109/DSD64264.2024.00061 %T DA-CGRA: Domain-Aware Heterogeneous Coarse-Grained Reconfigurable Architecture for the Edge %X Coarse-Grained Reconfigurable Architectures (CGRAs) are one of the promising solutions to be employed in power-hungry edge devices owing to providing a good balance between reconfigurability, performance and energy-efficiency. Most of the proposed CGRAs feature a homogeneous set of processing elements (PEs) which all support the same set of operations. Homogeneous PEs can lead to high unwanted power consumption. As application benchmarks utilize different operations irregularly, heterogeneous PE design is a powerful approach to reduce power consumption of CGRA. In this paper, we propose DA-CGRA, a domain-aware CGRA tailored to signal processing applications. To extract heterogeneous architecture, first, a set of signal processing applications has been profiled to derive the requirements of the applications in terms of type of operations, number of operations and memory usage. Then, domain-specific PEs are designed using Verilog RTL based on the profiling results. We have selected spatio-temporal or spatial execution model based on the application features to increase the overall performance and efficiency. Experimental results demonstrate DA-CGRA outperforms FLEX and RipTide state-of-the-art CGRAs in terms of energy-efficiency by 23% and 38%, respectively. Moreover, DA-CGRA can achieve 3.2x performance improvement over HM-HvCUBE.

@inproceedings{aliagha2024dacgra, abstract = {Coarse-Grained Reconfigurable Architectures (CGRAs) are one of the promising solutions to be employed in power-hungry edge devices owing to providing a good balance between reconfigurability, performance and energy-efficiency. Most of the proposed CGRAs feature a homogeneous set of processing elements (PEs) which all support the same set of operations. Homogeneous PEs can lead to high unwanted power consumption. As application benchmarks utilize different operations irregularly, heterogeneous PE design is a powerful approach to reduce power consumption of CGRA. In this paper, we propose DA-CGRA, a domain-aware CGRA tailored to signal processing applications. To extract heterogeneous architecture, first, a set of signal processing applications has been profiled to derive the requirements of the applications in terms of type of operations, number of operations and memory usage. Then, domain-specific PEs are designed using Verilog RTL based on the profiling results. We have selected spatio-temporal or spatial execution model based on the application features to increase the overall performance and efficiency. Experimental results demonstrate DA-CGRA outperforms FLEX and RipTide state-of-the-art CGRAs in terms of energy-efficiency by 23% and 38%, respectively. Moreover, DA-CGRA can achieve 3.2x performance improvement over HM-HvCUBE.}, added-at = {2024-12-20T11:18:52.000+0100}, author = {Aliagha, Ensieh and Charaf, Najdet and Venkatesan, Nitin Krishna and Göhringer, Diana}, biburl = {https://puma.scadsai.uni-leipzig.de/bibtex/26e8b6e8495fe27f06061240de0ee30dd/scadsfct}, booktitle = {2024 27th Euromicro Conference on Digital System Design (DSD)}, doi = {10.1109/DSD64264.2024.00061}, interhash = {b230825876ef64f727ce564743250137}, intrahash = {6e8b6e8495fe27f06061240de0ee30dd}, issn = {2771-2508}, keywords = {imported}, month = aug, pages = {410-417}, timestamp = {2024-12-20T11:18:52.000+0100}, title = {DA-CGRA: Domain-Aware Heterogeneous Coarse-Grained Reconfigurable Architecture for the Edge}, year = 2024 }